Verisity Launches Breakthrough Testbench Acceleration Technology

eCelerator is Powerful New Synthesis Technology for Accelerating Verification

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--March 4, 2002--Verisity Ltd. (Nasdaq: VRST - news), the leading provider of functional verification automation, today announced innovative new verification technology, eCelerator(TM). eCelerator is a testbench acceleration tool that enables the power of Specman Elite(TM) with the high performance of hardware-assisted verification. This provides users with a significant increase in verification performance while still taking advantage of an automated verification process. Testbench acceleration is the process of partitioning and synthesizing portions of the testbench to run on the hardware verification platform in order to optimize overall performance. This powerful new technology will initially support the following hardware emulation/acceleration systems - Palladium and CoBALT from Quickturn Design Systems a Cadence company, Celaro(TM) hardware emulator from Mentor Graphics®, and VStation from IKOS Systems.

eCelerator provides users with the ability to accelerate their verification by synthesizing and accelerating testbenches written in the e verification language. eCelerator synthesizes the most time-consuming parts of an e testbench onto the hardware, resulting in a dramatic increase in performance. Users retain access to all of the power in Specman Elite, providing them with a high degree of visibility into their design and complete consistency between their software simulations and accelerated simulations. This enables a single flow from simulation to emulation without requiring any changes to the e testbench.

"Specman Elite has captured a significant percentage of the market. As more people adopt testbench automation, the market for a solution like eCelerator becomes tremendously compelling. We've worked extremely closely with all three of our partners to develop this highly advanced technology to increase our customers' productivity and quality," said Moshe Gavrielov, chief executive officer for Verisity. "The testbench acceleration methodology opens up new markets for both Verisity and our hardware partners, while providing a solution that addresses a critical need for our customers."

"One of the biggest challenges of platform-based design is the size and complexity of the verification process," said John Goodenough, Global Design Methodology manager, ARM. "Verisity's eCelerator greatly expands our ability to use our standard Specman Elite-based methodology while taking advantage of high-performance hardware acceleration and emulation."

Evolution of Testbench Acceleration

Specman Elite has gained tremendous popularity among verification engineers because of its ability to automatically generate tests and perform checking and functional coverage analysis. Hardware verification solutions have typically only accelerated the RTL design. Not being able to accelerate these powerful testbenches caused a significant impact in the price performance value to customers who use hardware verification solutions. Because of this, hardware verification solutions were typically employed later in the verification cycle, where it's more difficult and costly to find and fix bugs. With eCelerator, the most time consuming portions of the e testbench are synthesized, greatly improving the price performance value and facilitating the use of hardware solutions earlier in the verification cycle.

eCelerator Technology

eCelerator synthesizes e code for acceleration and enables Specman Elite to interact directly with the hardware platforms. Through the use of constraints, users can easily indicate which portions of the testbench to target for synthesis. Using the proper methodology, a significant subset of e--almost anything that does not require dynamic allocation--can be synthesized including, bus functional models, monitors, data checkers, protocol checkers and error messaging. Since the e language is an easily layered, extensible language, it is easy to partition and synthesize legacy code.

Specman Elite interacts with the hardware platforms through a transaction-based interface. This open interface links the Specman Elite testbench directly with the synthesized e testbench running in the hardware, enabling Specman Elite to quickly send large amounts of data to the hardware and perform more comprehensive test runs. The user is able to configure the volume of transactions Specman Elite sends to the hardware, giving them more control over the performance on a per test basis. This enables the maximum throughput for regression test suites. Early benchmarking has shown a 10x to 60x improvement in performance.

"Combining these technologies into a single, highly integrated methodology is extremely powerful," said Francine Ferguson, vice president of worldwide marketing for Verisity. "Testbench acceleration provides users with what they need most: power and performance."

Promoting Verification Reuse

The testbench acceleration methodology can also be applied to verification reuse strategies. Verisity promotes verification reuse through the availability of e Verification Components (eVC(TM)s). eVCs are pre-verified, reusable plug-and-play verification environments for standard interfaces such as AMBA AHB, PCI and Ethernet. They drastically cut the time it takes to create a verification environment and get to first test in simulation. Accelerated eVCs are eVCs specifically developed for testbench acceleration, enabling these eVCs to be synthesized and accelerated on the hardware platform as well. The first accelerated eVC to be targeted for testbench acceleration is the AMBA AHB eVC from Verisity.

Availability

eCelerator will be available in limited release in the third quarter of 2002. The accelerated AHB eVC will be available in the fourth quarter of 2002.

About Verisity

Verisity is the leading provider of proprietary technologies and software products used to efficiently verify designs of electronic systems and complex integrated circuits that are essential to the communications and other high growth segments of the electronics industry. The Company's products automate the process of detecting flaws in these designs, enabling customers to deliver higher quality products, accelerate time-to-market and reduce overall product development costs.

Verisity Design, Inc.'s principal executive offices are located in Mountain View, CA. The Company's principal research and development offices are located in Rosh Ha'ain, Israel. For more information, see Verisity's web site at www.verisity.com.

Note to Editors: Verisity is a registered trademark of Verisity Design, Inc. eVC, eCelerator, and Specman Elite are trademarks of Verisity Design, Inc. All other trademarks are the property of their respected owners.

     Verisity Ltd.
     Jennifer Bilsey, 650/934-6823
     jen@verisity.com